Lower Voltage, Longer Lifespan... Seoul National University Develops Next-Generation Memory Device [Reading Science]

Operates at 0.6 V and withstands 1 trillion cycles... A step toward overcoming the speed-endurance trade-off
Ferroelectric interface design improves performance... Potential for low-power DRAM-type memory

A Seoul National University research team has developed a ferroelectric device for next-generation memory that operates quickly at low voltage and withstands 1 trillion cycles of repeated operation. The technology addresses a limitation of existing devices, whose lifespans shorten when memory operating speeds increase, and is expected to be used to develop next-generation DRAM-type memory with low power consumption.

The College of Engineering at Seoul National University announced on November 4 that a research team led by Professor Park Minhyeok of the Department of Materials Science and Engineering had developed a ferroelectric capacitor with ultra-low-voltage, high-speed and high-endurance characteristics in collaboration with researchers from Hanyang University, the Pohang Accelerator Laboratory and Samsung Electronics. The findings were published in the international journal Nature Communications.

A schematic of the structure and operating principles of a ferroelectric device for next-generation low-power memory developed by a research team led by Professor Park Minhyuk of Seoul National University. From left, it shows reduced voltage loss through interface engineering between the electrode and ferroelectric material, polarization switching at a low voltage of 0.6 V, and the potential to use a next-generation memory structure similar to DRAM. Provided by the research team.

Electrode and Interface Design Addresses Speed-Endurance Trade-Off

DRAM is a widely used type of memory found in computers, smartphones and artificial intelligence (AI) servers. It stores information by holding electrical charge in capacitors, but because the charge leaks over time, it requires a process called "refresh" to replenish the charge periodically. This process consumes power.

Ferroelectric memory, by contrast, stores information using "polarization," the electrical orientation within a material. Because this polarization state is maintained even when the power is turned off, ferroelectric memory can reduce the power consumed by refresh operations. However, writing information quickly requires high voltage, and increasing the voltage can shorten the device's lifespan.

The research team addressed this problem by precisely engineering the interface, the boundary where the ferroelectric material meets the electrode. The team used hafnium-zirconium oxide (HZO) as the ferroelectric material because it is highly compatible with existing semiconductor manufacturing processes.

The team controlled the crystal orientation and surface properties of the titanium nitride (TiN) electrode to suppress oxidation at the interface. This reduced voltage loss and enabled more uniform polarization switching within the ferroelectric material.

Operates at 0.6 V and Tested for 1 Trillion Cycles... Potential for DRAM-Type Memory

As a result, the team successfully switched polarization in a 5-nanometer (nm, one-billionth of a meter)-thick ferroelectric capacitor using a low voltage of 0.6 V. The time required to switch half of the polarization was about 42 nanoseconds (ns, one-billionth of a second) at 0.6 V and about 8.1 nanoseconds at 1 V.

The team also confirmed the device's performance under repeated operation. At both voltage levels, no dielectric breakdown occurred after 1 trillion cycles, and the different polarization states remained distinguishable. However, using a polarization performance decline of less than 20% as the benchmark, the device achieved endurance of 600 billion cycles at 0.6 V and 1 trillion cycles at 1 V.

The research team said that, compared with existing ferroelectric devices, the combination of low operating voltage, fast operation and high endurance represents world-leading performance.

The research team. (From left) Professor Park Minhyeok of Seoul National University (corresponding author), Professor Kim Hojun of Hanyang University (co-corresponding author), Professor Kwon Daeung of Hanyang University (co-corresponding author), and Park Geunhyeong, a postdoctoral researcher at Seoul National University's Institute of Semiconductor Research (first author). Provided by the College of Engineering at Seoul National University.

The team also demonstrated the potential for miniaturization. It found that polarization switching tended to become faster as the capacitor's area decreased. Based on this finding, the team predicted that reducing the device to the size used in actual DRAM could enable polarization switching at nanosecond speeds. However, this is an estimate based on experimental results, not performance verified in actual ultraminiature memory devices.

The team also proposed common-plate ferroelectric random-access memory (CP-FeRAM) using a "1T-1C" configuration comprising one transistor and one capacitor, as in DRAM. Circuit simulations based on the measured device characteristics confirmed the potential to distinguish information using residual polarization even after the stored charge had decreased.

The significance of the research lies in its simultaneous improvement of low-voltage, high-speed operation and endurance in ferroelectric memory, and in demonstrating the potential to apply the technology to a memory structure similar to existing DRAM. However, the research has not yet reached the stage of fabricating an actual memory chip, so further verification is needed, including of high-density circuit implementation and long-term data retention.

"This research is significant because, through electrode and interface design, it achieves three characteristics together: low voltage, fast operation and long lifespan. It also offers a solution to the trade-off between speed and endurance, a long-standing challenge for ferroelectric memory," said Professor Park Minhyeok of Seoul National University. "We expect the interface design and polarization-switching principles presented in this research to contribute to the development of low-power, high-density memory technologies."

This content was produced with the assistance of AI translation services.