Chips&Media Unveils 'Data Compression IP' to Resolve AI Semiconductor Memory Bottleneck

Chips&Media has unveiled its ‘Data Compression (DC) IP’ solution, which addresses the memory bottleneck in artificial intelligence (AI) semiconductors.

According to Chips&Media on October 7, the newly released Data Compression IP is the company’s first multimedia IP targeting applications beyond video. By losslessly compressing feature maps generated during AI computation, the solution alleviates memory bottlenecks in neural processing units (NPUs).

Chips&Media ran tests using key vision networks such as ResNet, MobileNet, and YOLO. The results showed that, depending on the data format, memory bandwidth savings reached 35.2% for FP16, 45.7% for BF16, and 53.5% for INT8. This, the company explained, expands the effective memory bandwidth available to NPUs in the same memory environment and enhances overall system processing efficiency.

User-friendliness for system integration has also been considered. The Data Compression IP is designed with an ‘inline AXI bridge’ structure, to be placed between existing NPUs and the AXI bus. Its lightweight architecture allows it to use the existing AXI clock without additional internal SRAM, minimizing increases in hardware footprint and enabling relatively straightforward integration into existing systems. The solution also supports various data formats—including INT8, FP16, and BF16—and features line-rate processing for fast data flows.

Currently, Chips&Media has completed development of the core feature map compression algorithm and C-model for the Data Compression IP and aims to finish hardware implementation by the first quarter of 2027. The company plans to broaden the range of applications for the Data Compression IP in line with customer needs and the characteristics of AI workloads. Starting with feature map compression, the product lineup will later expand to include Static Weight compression and, further, KV Cache compression—which is a primary cause of increased memory usage in large language models (LLMs) and vision language models (VLMs).

A Chips&Media representative stated, “Based on over 20 years of accumulated expertise in hardware IP design and our capabilities in optimizing power, size, and performance, we will maintain our competitive edge in the video codec market while expanding into the rapidly growing AI and high-performance multimedia IP sectors.”

This content was produced with the assistance of AI translation services.