Once Warped, Yields Plummet... The Hidden Threat That Could Decide Samsung and SK hynix's Semiconductor Supremacy [Chip Talk]

Advancing Memory and Ultra-Thin Chips Weaken Resistance to Pressure
"Serious Issue Even at the Packaging Stage"
Adoption of BSD in Front-End and Glass Substrates in Back-End Expected to Rise

As artificial intelligence (AI) semiconductors advance with each generation, they face a persistent and formidable challenge troubling global manufacturers: the "warpage" phenomenon, where semiconductor wafers become bent and crumpled like potato chips. If the physical distortion that occurs as chips are stacked higher and made thinner cannot be controlled, yields can plummet dramatically. Industry insiders believe that the fate of global semiconductor supremacy may hinge on which player can tame the warpage phenomenon first.

The Hidden Threat Undermining Chip Yields: Warpage

According to the industry on June 19, global memory manufacturers are currently grappling with defects caused by wafer warpage during the production of high bandwidth memory (HBM). With each new generation, HBM increases the number of stacked layers to achieve higher bandwidth and capacity, but as the individual dies are made thinner to maintain the overall package height, their ability to withstand external pressure or internal deformation inevitably weakens.

For HBM4 (6th generation), which Samsung Electronics and SK hynix are mass-producing, the Joint Electron Device Engineering Council (JEDEC) has relaxed the standard thickness to 775μm (micrometers), yet to stack 16 layers of DRAM in a limited space, each chip must be ground down to around 30μm—about one-third the thickness of a human hair. NAND flash memory has also reached more than 300 layers in three-dimensional structures, requiring the stacking of hundreds of ultrathin films. When mechanical stress accumulates on one side, the device becomes susceptible to the warpage phenomenon. The principle is similar to how a sheet of paper curls when too much glue is applied to one side.

Wafer warpage phenomenon. Semantic scalar

Junyoung Park, a researcher at Hanwha Investment & Securities, said, "Wafer warpage and the resulting decline in yield, especially for HBM4 and NAND, have been persistent issues recently," adding, "This is now a critical issue not only for the profitability of memory manufacturers but also for customers in terms of cost and delivery times."

Even if the warpage problem is resolved at the wafer stage, further challenges remain. During thermocompression (TC) bonding, when chips are joined together, and during packaging—where completed HBM chips are mounted onto substrates along with graphics processing units (GPUs) and central processing units (CPUs)—the so-called "warpage hell" can recur due to heat and pressure causing deformation. This is especially problematic for AI accelerators like NVIDIA's Rubin platform, which integrate large quantities of the latest HBM and generate substantial heat, making it difficult to maintain form without reinforcement using only conventional plastic (organic) substrates.

Changmin Yoon, professor of polymer engineering at Inha University, explained, "In reality, the warpage phenomenon is a much more severe problem during the packaging stage than in the front-end process," adding, "Materials used in back-end processes are much thicker than those in the front-end, and since printed circuit boards (PCBs), epoxy molding compounds (EMC), and underfill each have different coefficients of thermal expansion, warpage can occur hundreds of times more frequently."

What Is the Solution? BSD for the Front End, Glass Substrates for the Back End

In the front-end process, back-side deposition (BSD) equipment is emerging as a potential solution for the warpage issue. The principle is to deposit a compensating film on the wafer's back side, which applies a force in the opposite direction to the stress created by thin films on the front, thus mitigating warpage. It is akin to applying a balancing force to the reverse side of a sheet of paper curled by glue, straightening it out.

Researcher Park said, "As semiconductor technology advances toward thinner wafers and more complex structures, the adoption of BSD equipment to address warpage is expected to accelerate." He estimated that, based on monthly wafer input, NAND requires one BSD unit for every 2,500 to 3,000 wafers, and DRAM and HBM need one unit for every 5,000 to 7,000 wafers.

On the back-end side, glass substrates are cited as one of the keys to overcoming warpage. Conventional plastic-based organic substrates become more vulnerable to warpage as package sizes increase and high-temperature heat is applied. In contrast, glass has high heat resistance and a flat surface due to its material properties, helping suppress physical distortion. Above all, glass has a coefficient of thermal expansion similar to that of silicon chips, which can reduce warpage by more than 90% even at high temperatures, and its inherent rigidity helps maintain flatness even in large packages.

An industry representative said, "NVIDIA is continuing to use reinforced FC-BGA, which has proven productivity and marketability, for platforms like Blackwell and Vera Rubin. However, for next-generation products such as Rubin Ultra, where the number of chips will increase dramatically, the adoption of glass substrates will be actively considered."

Race to Secure Glass Substrates: Three-Way Competition in Korea

With glass substrates emerging as a game changer in the AI semiconductor market, related Korean companies are stepping up their efforts. As TSMC, the world's largest foundry, is reported to have achieved meaningful commercial validation of glass substrates, competition to gain early market dominance is expected to intensify.

Among domestic companies, SKC is considered the closest to commercializing glass substrates. Through its U.S. subsidiary Absolics, SKC has built the world's first dedicated glass substrate plant in Georgia and has dismissed concerns about scrapping its plans for a second U.S. plant, instead accelerating the build-out of its mass-production infrastructure. The company is currently supplying 'non-embedding' prototype products, which are structurally simple and advantageous for yield, to a U.S. communications semiconductor company for reliability testing. If validation is completed by the end of this year, SKC plans to begin full-scale commercialization in 2027.

Samsung Electro-Mechanics, which has a pilot production line in Sejong City, has established a turnkey system covering everything from materials to processes, thanks to its unique technology for precision drilling in glass. It is supplying glass substrate samples to global big tech customers with the goal of mass production after 2027. Competitor LG Innotek has also set up an R&D pilot line in Gumi and joined the technology development track.

An industry representative said, "The glass substrate market has moved beyond mere declarations of technological prowess and into a contest of tangible references—actual sample supply and passing customer qualification tests. Companies that secure entry as core consumables or materials in the global big tech manufacturing ecosystem and generate long-term, recurring revenue will ultimately dominate the market."

This content was produced with the assistance of AI translation services.