Jensen Huang Looks On as Samsung Unveils HBM5 Model for the First Time: "Will Meet Demands of Nvidia and Other Customers"

Application of HPB Thermal Management Technology to HBM5
First Unveiled at Computex 2026
2nm Process Foundry Base Die
CTO Song Jaehyuk: "Competitiveness as a Comprehensive Semiconductor Solution Provider"

Samsung Electronics unveiled the first physical model of its 8th generation High Bandwidth Memory (HBM5), expressing its determination to lead next-generation HBM technology.

Song Jaehyuk, Chief Technology Officer (CTO) of Samsung Electronics, met with reporters at the Samsung Display booth during 'Computex 2026' held in Taipei, Taiwan on the 2nd, stating, "Artificial Intelligence (AI) technology is not a single technology; it is crucial to optimize the entire system, including memory, packaging, and thermal management." He added, "As an integrated device manufacturer (IDM) with both memory and foundry (semiconductor contract manufacturing) capabilities, Samsung has the strength to optimize the whole system." He continued, "Through this, we will meet the demands of end customers, including Nvidia."

At this exhibition, Samsung Electronics officially showcased the HBM5 mockup for the first time and introduced the 'HPB (Heat Path Block)' structure, a core thermal management technology to be applied to HBM5 for the first time. Samsung plans to preemptively adopt a base die manufactured with its own 2nm (1nm = one billionth of a meter) foundry process for HBM5.

A physical model of 8th generation High Bandwidth Memory (HBM5) displayed at the Samsung Display booth during 'COMPUTEX 2026' held in Taipei, Taiwan on the 2nd. Photo by Jinyoung Kim.

HPB is a technology designed to resolve heat generation issues that may arise while improving AI memory performance, enabling more efficient dissipation and release of heat from the physical surfaces between dies. Samsung Electronics has already completed the implementation and verification of HPB technology based on HBM4E. Starting with HBM5, the company plans to fully apply this technology to further enhance performance and stability.

CTO Song stated, "For HBM5, we will introduce the advanced 2nm process to optimize the base die," and added, "We are preparing to provide the bandwidth and power efficiency demanded by the market." He further explained, "The development achievements accumulated over the three to four years since the adoption of Gate-All-Around (GAA) technology are showing promising results," and emphasized, "We will secure differentiated competitiveness through this."

Song Jaehyuk, Chief Technology Officer (CTO) of Samsung Electronics, is answering questions from reporters at the Samsung Display booth during Computex 2026 held in Taipei, Taiwan, on the 2nd (local time). Photo by Kim Jinyoung.

In particular, Samsung also disclosed the current status of applying hybrid bonding technology, which is considered a key next-generation HBM technology. CTO Song explained, "Hybrid bonding is a technology that directly connects without gaps, allowing for reduced connection pad spacing and improved bandwidth," and emphasized, "While conventional TCB is a packaging technology, hybrid bonding is a silicon process-based technology, which is one of Samsung's strengths."

Regarding the next-generation HBM stacking structure, he said, "We are considering 12-layer, 16-layer, and 20-layer stacking," and added, "We are developing technology to meet customer demands for increased memory capacity."

Additionally, CTO Song commented on the direction of semiconductor advanced process development, stating, "We are preparing in terms of equipment, materials, and ecosystem to advance below the 1nm threshold," and added, "We believe sub-1nm processing is also achievable."

Samsung Electronics' wafer and chipset of HBM4E displayed at the Samsung Display booth at 'Computex 2026' held in Taipei, Taiwan on the 2nd. Photo by Jin-Young Kim.

At the exhibition, Samsung Electronics also unveiled the wafer and chipset of HBM4E, for which it completed industry-first sample shipments at the end of last month. Samsung Electronics' HBM4E combines the most advanced 1c DRAM core die with its own foundry 4nm process base die, operating at 14Gbps (gigabits per second) per pin and achieving up to 16Gbps (maximum 4TB/s bandwidth).

This content was produced with the assistance of AI translation services.