KOREATECH Selected for 10 Billion Won Semiconductor Packaging Project

Selected for Infrastructure Development Project

Strengthening Semiconductor Competitiveness

Korea University of Technology and Education (KOREATECH) will receive 10 billion won in government funding to establish next-generation semiconductor packaging process and evaluation infrastructure.

Aerial view of the TU Research Park at Korea Polytechnic University. Korea Polytechnic University

On May 26, KOREATECH announced that it had been selected as the final implementing institution for the project, "Establishing Process and Evaluation Infrastructure to Respond to Large-Area Packaging Miniaturization," which is part of the Industrial Innovation Infrastructure Development Program led by the Ministry of Trade, Industry and Energy and the Korea Institute for Advancement of Technology (KIAT).

This project aims to meet the demand for advanced chiplet-based packaging driven by the expansion of the artificial intelligence (AI) semiconductor and high-performance computing (HPC) markets. The government plans to build a foundation capable of integrated demonstration of ultra-fine circuit processing at a 3-micrometer (μm) pitch and quantitative evaluation on large-area panels of 500×500 mm² or more.

As the lead institution, KOREATECH will receive 10 billion won in government funding over the next five years to build process lines, develop evaluation technologies, and establish a corporate support system.

KOREATECH has formed a consortium centered on its Shared Equipment Center, joining forces with the Korea Institute of Industrial Technology, Korea Electronics Technology Institute, and the Materials, Parts & Equipment Technology Convergence Research Association. The participating organizations will integrate their equipment and research capabilities to support process development and evaluation in semiconductor packaging.

Through this project, KOREATECH will establish a large-area ultra-fine processing line for 510×515 mm² panels. The project also aims to advance semi-additive process (SAP)-based fine patterning, establish a high-resolution automatic optical inspection (AOI)-based comprehensive quantitative evaluation system, and develop multilayer redistribution layer (RDL) and high-frequency characteristic evaluation technologies.

A one-stop integrated support system for companies will also be set up. KOREATECH plans to link its existing semiconductor packaging infrastructure with this project to operate an industry-academia-research cooperation platform for process development, evaluation, demonstration, and technical support.

This project will build both ultra-fine processing and quantitative evaluation systems in the panel-based semiconductor packaging sector. The established infrastructure will be utilized for developing advanced packaging technologies for AI and HPC applications, as well as for process verification, prototype production, and performance evaluation by domestic companies.

Kim Kyungmin, Professor in the Department of Advanced Materials Engineering at KOREATECH, said, "Being selected for this project will serve as a springboard for KOREATECH to become a core research hub in the field of advanced semiconductor packaging. By building large-area ultra-fine process and evaluation infrastructure, we will support domestic companies in securing globally competitive advanced packaging technologies."

This content was produced with the assistance of AI translation services.